| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172 |
- 1 ; C Compiler for STM8 (COSMIC Software)
- 2 ; Parser V4.8.32 - 23 Mar 2010
- 3 ; Generator V4.3.4 - 23 Mar 2010
- 2731 ; 5 void TIM2_INIT(void)
- 2731 ; 6 {
- 2733 switch .text
- 2734 0000 _TIM2_INIT:
- 2738 ; 8 TURN_OUT_DDR = 1;//1: 输出模式
- 2740 0000 721a500c bset _TURN_OUT_DDR
- 2741 ; 9 TURN_OUT_CR1 = 1;//1：推挽输出,
- 2743 0004 721a500d bset _TURN_OUT_CR1
- 2744 ; 10 TURN_OUT_CR2 = 1;//1：输出速度最大为10MHZ
- 2746 0008 721a500e bset _TURN_OUT_CR2
- 2747 ; 11 TURN_OUT_ODR = 0;
- 2749 000c 721b500a bres _TURN_OUT_ODR
- 2750 ; 14 CLK_PCKENR1 |= 0x20;
- 2752 0010 721a50c7 bset _CLK_PCKENR1,#5
- 2753 ; 16 TIM2_PSCR = 0x00; //定时器2预分频系数为1
- 2755 0014 725f530e clr _TIM2_PSCR
- 2756 ; 19 TIM2_ARRH = 0x03;//0320，10K
- 2758 0018 3503530f mov _TIM2_ARRH,#3
- 2759 ; 20 TIM2_ARRL = 0x20;//
- 2761 001c 35205310 mov _TIM2_ARRL,#32
- 2762 ; 22 TIM2_CCMR1 |= 0X68;
- 2764 0020 c65307 ld a,_TIM2_CCMR1
- 2765 0023 aa68 or a,#104
- 2766 0025 c75307 ld _TIM2_CCMR1,a
- 2767 ; 23 TIM2_CCER1 |= 0x01; //开启OC1信号输出脚--高电平有效
- 2769 0028 7210530a bset _TIM2_CCER1,#0
- 2770 ; 28 TIM2_CCR1H = 0x01; //占空比 50%--2
- 2772 002c 35015311 mov _TIM2_CCR1H,#1
- 2773 ; 29 TIM2_CCR1L = 0x99;
- 2775 0030 35995312 mov _TIM2_CCR1L,#153
- 2776 ; 44 TIM2_CR1 = 0x00;
- 2778 0034 725f5300 clr _TIM2_CR1
- 2779 ; 45 }
- 2782 0038 81 ret
- 2818 ; 47 void TIM2_PWM(char v)
- 2818 ; 48 {
- 2819 switch .text
- 2820 0039 _TIM2_PWM:
- 2824 ; 49 switch(v)
- 2827 ; 61 default:
- 2827 ; 62 break;
- 2828 0039 4d tnz a
- 2829 003a 270d jreq L7271
- 2830 003c 4a dec a
- 2831 003d 2612 jrne L3571
- 2832 ; 51 case 1:
- 2832 ; 52 //CLK_PCKENR1 |= 0x20;
- 2832 ; 53 TIM2_CCER1 |= 0x01;//开启OC1信号输出脚--低电平有效
- 2834 003f 7210530a bset _TIM2_CCER1,#0
- 2835 ; 54 TIM2_CR1 = 0x01;
- 2837 0043 35015300 mov _TIM2_CR1,#1
- 2838 ; 55 break;
- 2840 0047 2008 jra L3571
- 2841 0049 L7271:
- 2842 ; 56 case 0:
- 2842 ; 57 TIM2_CR1 = 0x00;
- 2844 0049 725f5300 clr _TIM2_CR1
- 2845 ; 58 TIM2_CCER1 &= ~0x01;
- 2847 004d 7211530a bres _TIM2_CCER1,#0
- 2848 ; 60 break;
- 2850 0051 L1371:
- 2851 ; 61 default:
- 2851 ; 62 break;
- 2853 0051 L3571:
- 2854 ; 64 }
- 2857 0051 81 ret
- 2870 xdef _TIM2_PWM
- 2871 xdef _TIM2_INIT
- 2890 end
|
