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- 1 ; C Compiler for STM8 (COSMIC Software)
- 2 ; Parser V4.8.32 - 23 Mar 2010
- 3 ; Generator V4.3.4 - 23 Mar 2010
- 2738 ; 6 void TIM1_INIT(void)
- 2738 ; 7 {
- 2740 switch .text
- 2741 0000 _TIM1_INIT:
- 2745 ; 9 CLK_PCKENR1 |= 0x80;
- 2747 0000 721e50c7 bset _CLK_PCKENR1,#7
- 2748 ; 11 TIM1_PSCRH = 0x00; //定时器1预分频系数为1
- 2750 0004 725f5260 clr _TIM1_PSCRH
- 2751 ; 12 TIM1_PSCRL = 0x00;
- 2753 0008 725f5261 clr _TIM1_PSCRL
- 2754 ; 14 TIM1_ARRH = 0x00;//0320，10K
- 2756 000c 725f5262 clr _TIM1_ARRH
- 2757 ; 15 TIM1_ARRL = 0x10;//
- 2759 0010 35105263 mov _TIM1_ARRL,#16
- 2760 ; 19 TIM1_CNTRH = 0;
- 2762 0014 725f525e clr _TIM1_CNTRH
- 2763 ; 20 TIM1_CNTRL = 0;
- 2765 0018 725f525f clr _TIM1_CNTRL
- 2766 ; 31 TIM1_CR1 |= 1<<7;//允许重装，使能定时器
- 2768 001c 721e5250 bset _TIM1_CR1,#7
- 2769 ; 32 TIM1_CR1 |= 1<<4;//选择向下计数模式
- 2771 0020 72185250 bset _TIM1_CR1,#4
- 2772 ; 33 TIM1_CR1 &= ~(1<<0);//使能计数器
- 2774 0024 72115250 bres _TIM1_CR1,#0
- 2775 ; 34 }
- 2778 0028 81 ret
- 2781 bsct
- 2782 0000 _tmp:
- 2783 0000 00 dc.b 0
- 2806 ; 38 @far @interrupt void TIM1_UPD_IRQ(void)
- 2806 ; 39 {
- 2808 switch .text
- 2809 0029 f_TIM1_UPD_IRQ:
- 2813 ; 43 tmp = TIM1_SR1&0x01;
- 2815 0029 c65255 ld a,_TIM1_SR1
- 2816 002c a401 and a,#1
- 2817 002e b700 ld _tmp,a
- 2818 ; 45 }
- 2821 0030 80 iret
- 2860 ; 47 void _delay_us(int time)
- 2860 ; 48 {
- 2862 switch .text
- 2863 0031 __delay_us:
- 2865 0031 89 pushw x
- 2866 00000000 OFST: set 0
- 2869 ; 54 TIM1_ARRH = 0x00;//
- 2871 0032 725f5262 clr _TIM1_ARRH
- 2872 ; 55 TIM1_ARRL = 0x10;//
- 2874 0036 35105263 mov _TIM1_ARRL,#16
- 2875 ; 58 TIM1_CNTRH = 0;
- 2877 003a 725f525e clr _TIM1_CNTRH
- 2878 ; 59 TIM1_CNTRL = 0;
- 2880 003e 725f525f clr _TIM1_CNTRL
- 2881 ; 62 TIM1_CR1 = 0x01;
- 2883 0042 35015250 mov _TIM1_CR1,#1
- 2885 0046 2004 jra L3671
- 2886 0048 L7571:
- 2887 ; 66 TIM1_SR1 = 0x00;
- 2889 0048 725f5255 clr _TIM1_SR1
- 2890 004c L3671:
- 2891 ; 63 while(time--)
- 2893 004c 1e01 ldw x,(OFST+1,sp)
- 2894 004e 1d0001 subw x,#1
- 2895 0051 1f01 ldw (OFST+1,sp),x
- 2896 0053 1c0001 addw x,#1
- 2897 0056 a30000 cpw x,#0
- 2898 0059 26ed jrne L7571
- 2899 ; 68 TIM1_CR1 = 0x00;
- 2901 005b 725f5250 clr _TIM1_CR1
- 2902 ; 69 }
- 2905 005f 85 popw x
- 2906 0060 81 ret
- 2946 ; 71 void _delay_50us(int time)
- 2946 ; 72 {
- 2947 switch .text
- 2948 0061 __delay_50us:
- 2950 0061 89 pushw x
- 2951 00000000 OFST: set 0
- 2954 ; 74 TIM1_ARRH = 0x03;
- 2956 0062 35035262 mov _TIM1_ARRH,#3
- 2957 ; 75 TIM1_ARRL = 0x20;
- 2959 0066 35205263 mov _TIM1_ARRL,#32
- 2960 ; 77 TIM1_CNTRH = 0;
- 2962 006a 725f525e clr _TIM1_CNTRH
- 2963 ; 78 TIM1_CNTRL = 0;
- 2965 006e 725f525f clr _TIM1_CNTRL
- 2966 ; 82 TIM1_CR1 |= 1<<0;//使能计数器
- 2968 0072 72105250 bset _TIM1_CR1,#0
- 2970 0076 2004 jra L7002
- 2971 0078 L5002:
- 2972 ; 86 TIM1_SR1 = 0x00;
- 2974 0078 725f5255 clr _TIM1_SR1
- 2975 007c L7002:
- 2976 ; 83 while(time--)
- 2978 007c 1e01 ldw x,(OFST+1,sp)
- 2979 007e 1d0001 subw x,#1
- 2980 0081 1f01 ldw (OFST+1,sp),x
- 2981 0083 1c0001 addw x,#1
- 2982 0086 a30000 cpw x,#0
- 2983 0089 26ed jrne L5002
- 2984 ; 89 TIM1_CR1 &= ~(1<<0);
- 2986 008b 72115250 bres _TIM1_CR1,#0
- 2987 ; 90 }
- 2990 008f 85 popw x
- 2991 0090 81 ret
- 3031 ; 92 void _delay_1ms(int time)
- 3031 ; 93 {
- 3032 switch .text
- 3033 0091 __delay_1ms:
- 3037 ; 95 TIM1_ARRH = 0x3e;
- 3039 0091 353e5262 mov _TIM1_ARRH,#62
- 3040 ; 96 TIM1_ARRL = 0x80;
- 3042 0095 35805263 mov _TIM1_ARRL,#128
- 3043 ; 98 TIM1_CNTRH = 0;
- 3045 0099 725f525e clr _TIM1_CNTRH
- 3046 ; 99 TIM1_CNTRL = 0;
- 3048 009d 725f525f clr _TIM1_CNTRL
- 3049 ; 105 TIM1_CR1 &= ~(1<<0);//使能计数器
- 3051 00a1 72115250 bres _TIM1_CR1,#0
- 3052 ; 109 TIM1_SR1 = 0x00;
- 3054 00a5 725f5255 clr _TIM1_SR1
- 3055 ; 112 TIM1_CR1 &= ~(1<<0);
- 3057 00a9 72115250 bres _TIM1_CR1,#0
- 3058 ; 113 }
- 3061 00ad 81 ret
- 3102 ; 119 void TIM1_PWM_INIT(void)
- 3102 ; 120 {
- 3103 switch .text
- 3104 00ae _TIM1_PWM_INIT:
- 3108 ; 122 PC6_DDR = 1; //PC6配置为输出
- 3110 00ae 721c500c bset _PC6_DDR
- 3111 ; 123 PC6_CR1 = 1; //推挽输出
- 3113 00b2 721c500d bset _PC6_CR1
- 3114 ; 124 PC6_CR2 = 1; //高速输出
- 3116 00b6 721c500e bset _PC6_CR2
- 3117 ; 127 PC7_DDR = 1; //PC7配置为输出
- 3119 00ba 721e500c bset _PC7_DDR
- 3120 ; 128 PC7_CR1 = 1; //推挽输出
- 3122 00be 721e500d bset _PC7_CR1
- 3123 ; 129 PC7_CR2 = 1; //高速输出
- 3125 00c2 721e500e bset _PC7_CR2
- 3126 ; 169 TIM1_CR1 &= ~BIT(0); //关闭TIM1
- 3128 00c6 72115250 bres _TIM1_CR1,#0
- 3129 ; 171 TIM1_PSCRH = 0;
- 3131 00ca 725f5260 clr _TIM1_PSCRH
- 3132 ; 172 TIM1_PSCRL = 0; //不分频8MHz
- 3134 00ce 725f5261 clr _TIM1_PSCRL
- 3135 ; 175 TIM1_ARRH = 0X1f;
- 3137 00d2 351f5262 mov _TIM1_ARRH,#31
- 3138 ; 176 TIM1_ARRL = 0X40; //8MHz/1k = 8000==0x1f 4000--0fa0
- 3140 00d6 35405263 mov _TIM1_ARRL,#64
- 3141 ; 178 TIM1_CR1 |= BIT(7); //使能ARP,边沿对齐，向上计数
- 3143 00da 721e5250 bset _TIM1_CR1,#7
- 3144 ; 179 TIM1_EGR |= BIT(0); //更新TIM1，使PSC有效
- 3146 00de 72105257 bset _TIM1_EGR,#0
- 3147 ; 180 TIM1_EGR |= 0x20; //重新初始化TIM1
- 3149 00e2 721a5257 bset _TIM1_EGR,#5
- 3150 ; 189 TIM1_CCR1H = 0X09; //2500---占空比25/80---13v
- 3152 00e6 35095265 mov _TIM1_CCR1H,#9
- 3153 ; 190 TIM1_CCR1L = 0Xc4;
- 3155 00ea 35c45266 mov _TIM1_CCR1L,#196
- 3156 ; 194 TIM1_CCMR1 = 0X68; //配置TIM1_CH1为PWM1模式输出
- 3158 00ee 35685258 mov _TIM1_CCMR1,#104
- 3159 ; 204 TIM1_CCR2H = 0X09;
- 3161 00f2 35095267 mov _TIM1_CCR2H,#9
- 3162 ; 205 TIM1_CCR2L = 0Xc4; //2500---占空比25/80---13v
- 3164 00f6 35c45268 mov _TIM1_CCR2L,#196
- 3165 ; 209 TIM1_CCMR2 = 0X68; //配置TIM1_CH2为PWM1模式输出
- 3167 00fa 35685259 mov _TIM1_CCMR2,#104
- 3168 ; 219 }
- 3171 00fe 81 ret
- 3197 ; 221 void TG_UP(void)
- 3197 ; 222 {
- 3198 switch .text
- 3199 00ff _TG_UP:
- 3203 ; 223 TIM1_CCER1 |= BIT(0); //Enable TIM1_CH1 channel
- 3205 00ff 7210525c bset _TIM1_CCER1,#0
- 3206 ; 225 TIM1_BKR |= BIT(7); //
- 3208 0103 721e526d bset _TIM1_BKR,#7
- 3209 ; 226 TIM1_CR1 |= BIT(0); //使能TIM1
- 3211 0107 72105250 bset _TIM1_CR1,#0
- 3212 ; 227 }
- 3215 010b 81 ret
- 3241 ; 229 void TG_DW(void)
- 3241 ; 230 {
- 3242 switch .text
- 3243 010c _TG_DW:
- 3247 ; 232 TIM1_CCER1 |= BIT(4); //Enable TIM1_CH2 channel
- 3249 010c 7218525c bset _TIM1_CCER1,#4
- 3250 ; 233 TIM1_BKR |= BIT(7); //
- 3252 0110 721e526d bset _TIM1_BKR,#7
- 3253 ; 234 TIM1_CR1 |= BIT(0); //使能TIM1
- 3255 0114 72105250 bset _TIM1_CR1,#0
- 3256 ; 235 }
- 3259 0118 81 ret
- 3285 ; 237 void TG_STOP(void)
- 3285 ; 238 {
- 3286 switch .text
- 3287 0119 _TG_STOP:
- 3291 ; 239 TIM1_BKR = 7; //
- 3293 0119 3507526d mov _TIM1_BKR,#7
- 3294 ; 240 TIM1_CR1 &= ~BIT(0); //关闭TIM1
- 3296 011d 72115250 bres _TIM1_CR1,#0
- 3297 ; 241 TIM1_CCER1 = 0; //disable TIM1_CH1 channel
- 3299 0121 725f525c clr _TIM1_CCER1
- 3300 ; 242 }
- 3303 0125 81 ret
- 3327 xdef f_TIM1_UPD_IRQ
- 3328 xdef _tmp
- 3329 xdef _TG_STOP
- 3330 xdef _TG_DW
- 3331 xdef _TG_UP
- 3332 xdef _TIM1_PWM_INIT
- 3333 xdef __delay_1ms
- 3334 xdef __delay_50us
- 3335 xdef __delay_us
- 3336 xdef _TIM1_INIT
- 3355 end
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