1 ; C Compiler for STM8 (COSMIC Software) 2 ; Parser V4.8.32 - 23 Mar 2010 3 ; Generator V4.3.4 - 23 Mar 2010 2726 ; 6 void TIM1_INIT(void) 2726 ; 7 { 2728 switch .text 2729 0000 _TIM1_INIT: 2733 ; 9 CLK_PCKENR1 |= 0x80; 2735 0000 721e50c7 bset _CLK_PCKENR1,#7 2736 ; 11 TIM1_PSCRH = 0x00; //定时器1预分频系数为1 2738 0004 725f5260 clr _TIM1_PSCRH 2739 ; 12 TIM1_PSCRL = 0x00; 2741 0008 725f5261 clr _TIM1_PSCRL 2742 ; 14 TIM1_ARRH = 0x00;//0320，10K 2744 000c 725f5262 clr _TIM1_ARRH 2745 ; 15 TIM1_ARRL = 0x10;// 2747 0010 35105263 mov _TIM1_ARRL,#16 2748 ; 19 TIM1_CNTRH = 0; 2750 0014 725f525e clr _TIM1_CNTRH 2751 ; 20 TIM1_CNTRL = 0; 2753 0018 725f525f clr _TIM1_CNTRL 2754 ; 31 TIM1_CR1 |= 1<<7;//允许重装，使能定时器 2756 001c 721e5250 bset _TIM1_CR1,#7 2757 ; 32 TIM1_CR1 |= 1<<4;//选择向下计数模式 2759 0020 72185250 bset _TIM1_CR1,#4 2760 ; 33 TIM1_CR1 &= ~(1<<0);//使能计数器 2762 0024 72115250 bres _TIM1_CR1,#0 2763 ; 34 } 2766 0028 81 ret 2769 bsct 2770 0000 _tmp: 2771 0000 00 dc.b 0 2794 ; 38 @far @interrupt void TIM1_UPD_IRQ(void) 2794 ; 39 { 2796 switch .text 2797 0029 f_TIM1_UPD_IRQ: 2801 ; 43 tmp = TIM1_SR1&0x01; 2803 0029 c65255 ld a,_TIM1_SR1 2804 002c a401 and a,#1 2805 002e b700 ld _tmp,a 2806 ; 45 } 2809 0030 80 iret 2848 ; 47 void _delay_us(int time) 2848 ; 48 { 2850 switch .text 2851 0031 __delay_us: 2853 0031 89 pushw x 2854 00000000 OFST: set 0 2857 ; 54 TIM1_ARRH = 0x00;// 2859 0032 725f5262 clr _TIM1_ARRH 2860 ; 55 TIM1_ARRL = 0x10;// 2862 0036 35105263 mov _TIM1_ARRL,#16 2863 ; 58 TIM1_CNTRH = 0; 2865 003a 725f525e clr _TIM1_CNTRH 2866 ; 59 TIM1_CNTRL = 0; 2868 003e 725f525f clr _TIM1_CNTRL 2869 ; 62 TIM1_CR1 = 0x01; 2871 0042 35015250 mov _TIM1_CR1,#1 2873 0046 2004 jra L7571 2874 0048 L3571: 2875 ; 66 TIM1_SR1 = 0x00; 2877 0048 725f5255 clr _TIM1_SR1 2878 004c L7571: 2879 ; 63 while(time--) 2881 004c 1e01 ldw x,(OFST+1,sp) 2882 004e 1d0001 subw x,#1 2883 0051 1f01 ldw (OFST+1,sp),x 2884 0053 1c0001 addw x,#1 2885 0056 a30000 cpw x,#0 2886 0059 26ed jrne L3571 2887 ; 68 TIM1_CR1 = 0x00; 2889 005b 725f5250 clr _TIM1_CR1 2890 ; 69 } 2893 005f 85 popw x 2894 0060 81 ret 2934 ; 71 void _delay_50us(int time) 2934 ; 72 { 2935 switch .text 2936 0061 __delay_50us: 2938 0061 89 pushw x 2939 00000000 OFST: set 0 2942 ; 74 TIM1_ARRH = 0x03; 2944 0062 35035262 mov _TIM1_ARRH,#3 2945 ; 75 TIM1_ARRL = 0x20; 2947 0066 35205263 mov _TIM1_ARRL,#32 2948 ; 77 TIM1_CNTRH = 0; 2950 006a 725f525e clr _TIM1_CNTRH 2951 ; 78 TIM1_CNTRL = 0; 2953 006e 725f525f clr _TIM1_CNTRL 2954 ; 82 TIM1_CR1 |= 1<<0;//使能计数器 2956 0072 72105250 bset _TIM1_CR1,#0 2958 0076 2004 jra L3002 2959 0078 L1002: 2960 ; 86 TIM1_SR1 = 0x00; 2962 0078 725f5255 clr _TIM1_SR1 2963 007c L3002: 2964 ; 83 while(time--) 2966 007c 1e01 ldw x,(OFST+1,sp) 2967 007e 1d0001 subw x,#1 2968 0081 1f01 ldw (OFST+1,sp),x 2969 0083 1c0001 addw x,#1 2970 0086 a30000 cpw x,#0 2971 0089 26ed jrne L1002 2972 ; 89 TIM1_CR1 &= ~(1<<0); 2974 008b 72115250 bres _TIM1_CR1,#0 2975 ; 90 } 2978 008f 85 popw x 2979 0090 81 ret 3019 ; 92 void _delay_1ms(int time) 3019 ; 93 { 3020 switch .text 3021 0091 __delay_1ms: 3025 ; 95 TIM1_ARRH = 0x3e; 3027 0091 353e5262 mov _TIM1_ARRH,#62 3028 ; 96 TIM1_ARRL = 0x80; 3030 0095 35805263 mov _TIM1_ARRL,#128 3031 ; 98 TIM1_CNTRH = 0; 3033 0099 725f525e clr _TIM1_CNTRH 3034 ; 99 TIM1_CNTRL = 0; 3036 009d 725f525f clr _TIM1_CNTRL 3037 ; 105 TIM1_CR1 &= ~(1<<0);//使能计数器 3039 00a1 72115250 bres _TIM1_CR1,#0 3040 ; 109 TIM1_SR1 = 0x00; 3042 00a5 725f5255 clr _TIM1_SR1 3043 ; 112 TIM1_CR1 &= ~(1<<0); 3045 00a9 72115250 bres _TIM1_CR1,#0 3046 ; 113 } 3049 00ad 81 ret 3090 ; 119 void TIM1_PWM_INIT(void) 3090 ; 120 { 3091 switch .text 3092 00ae _TIM1_PWM_INIT: 3096 ; 122 PC6_DDR = 1; //PC6配置为输出 3098 00ae 721c500c bset _PC6_DDR 3099 ; 123 PC6_CR1 = 1; //推挽输出 3101 00b2 721c500d bset _PC6_CR1 3102 ; 124 PC6_CR2 = 1; //高速输出 3104 00b6 721c500e bset _PC6_CR2 3105 ; 127 PC7_DDR = 1; //PC7配置为输出 3107 00ba 721e500c bset _PC7_DDR 3108 ; 128 PC7_CR1 = 1; //推挽输出 3110 00be 721e500d bset _PC7_CR1 3111 ; 129 PC7_CR2 = 1; //高速输出 3113 00c2 721e500e bset _PC7_CR2 3114 ; 169 TIM1_CR1 &= ~BIT(0); //关闭TIM1 3116 00c6 72115250 bres _TIM1_CR1,#0 3117 ; 171 TIM1_PSCRH = 0; 3119 00ca 725f5260 clr _TIM1_PSCRH 3120 ; 172 TIM1_PSCRL = 0; //不分频8MHz 3122 00ce 725f5261 clr _TIM1_PSCRL 3123 ; 175 TIM1_ARRH = 0X1f; 3125 00d2 351f5262 mov _TIM1_ARRH,#31 3126 ; 176 TIM1_ARRL = 0X40; //8MHz/1k = 8000==0x1f 4000--0fa0 3128 00d6 35405263 mov _TIM1_ARRL,#64 3129 ; 178 TIM1_CR1 |= BIT(7); //使能ARP,边沿对齐，向上计数 3131 00da 721e5250 bset _TIM1_CR1,#7 3132 ; 179 TIM1_EGR |= BIT(0); //更新TIM1，使PSC有效 3134 00de 72105257 bset _TIM1_EGR,#0 3135 ; 180 TIM1_EGR |= 0x20; //重新初始化TIM1 3137 00e2 721a5257 bset _TIM1_EGR,#5 3138 ; 189 TIM1_CCR1H = 0X09; //2500---占空比25/80---13v 3140 00e6 35095265 mov _TIM1_CCR1H,#9 3141 ; 190 TIM1_CCR1L = 0Xc4; 3143 00ea 35c45266 mov _TIM1_CCR1L,#196 3144 ; 194 TIM1_CCMR1 = 0X68; //配置TIM1_CH1为PWM1模式输出 3146 00ee 35685258 mov _TIM1_CCMR1,#104 3147 ; 204 TIM1_CCR2H = 0X09; 3149 00f2 35095267 mov _TIM1_CCR2H,#9 3150 ; 205 TIM1_CCR2L = 0Xc4; //2500---占空比25/80---13v 3152 00f6 35c45268 mov _TIM1_CCR2L,#196 3153 ; 209 TIM1_CCMR2 = 0X68; //配置TIM1_CH2为PWM1模式输出 3155 00fa 35685259 mov _TIM1_CCMR2,#104 3156 ; 219 } 3159 00fe 81 ret 3185 ; 221 void TG_UP(void) 3185 ; 222 { 3186 switch .text 3187 00ff _TG_UP: 3191 ; 223 TIM1_CCER1 |= BIT(0); //Enable TIM1_CH1 channel 3193 00ff 7210525c bset _TIM1_CCER1,#0 3194 ; 225 TIM1_BKR |= BIT(7); // 3196 0103 721e526d bset _TIM1_BKR,#7 3197 ; 226 TIM1_CR1 |= BIT(0); //使能TIM1 3199 0107 72105250 bset _TIM1_CR1,#0 3200 ; 227 } 3203 010b 81 ret 3229 ; 229 void TG_DW(void) 3229 ; 230 { 3230 switch .text 3231 010c _TG_DW: 3235 ; 232 TIM1_CCER1 |= BIT(4); //Enable TIM1_CH2 channel 3237 010c 7218525c bset _TIM1_CCER1,#4 3238 ; 233 TIM1_BKR |= BIT(7); // 3240 0110 721e526d bset _TIM1_BKR,#7 3241 ; 234 TIM1_CR1 |= BIT(0); //使能TIM1 3243 0114 72105250 bset _TIM1_CR1,#0 3244 ; 235 } 3247 0118 81 ret 3273 ; 237 void TG_STOP(void) 3273 ; 238 { 3274 switch .text 3275 0119 _TG_STOP: 3279 ; 239 TIM1_BKR = 7; // 3281 0119 3507526d mov _TIM1_BKR,#7 3282 ; 240 TIM1_CR1 &= ~BIT(0); //关闭TIM1 3284 011d 72115250 bres _TIM1_CR1,#0 3285 ; 241 TIM1_CCER1 = 0; //disable TIM1_CH1 channel 3287 0121 725f525c clr _TIM1_CCER1 3288 ; 242 } 3291 0125 81 ret 3315 xdef f_TIM1_UPD_IRQ 3316 xdef _tmp 3317 xdef _TG_STOP 3318 xdef _TG_DW 3319 xdef _TG_UP 3320 xdef _TIM1_PWM_INIT 3321 xdef __delay_1ms 3322 xdef __delay_50us 3323 xdef __delay_us 3324 xdef _TIM1_INIT 3343 end